What is Co-Packaged Optics (CPO)?

The Evolution of Optical Interconnects

For decades, data center networks relied on pluggable optical transceivers—separate modules that connected to switches via fiber cables. As bandwidth demands grew from 10G to 400G and beyond, the limitations of this approach became apparent: excessive power consumption, signal latency at the switch-to-optics interface, and density constraints.

Co-Packaged Optics (CPO) represents a fundamental architectural shift: instead of placing optics as separate pluggable modules, the optical engines are integrated directly into the switch package, adjacent to the ASIC.

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Why CPO Matters for AI Infrastructure

The Bandwidth Challenge

AI clusters require massive bandwidth between GPUs and switches. A modern AI cluster with 16,000 GPUs might need 12.8 Pbps of aggregate bandwidth—equivalent to connecting every person in Shanghai simultaneously at 1Mbps each.

Traditional pluggable optics struggle to meet this demand efficiently:

• Power: 400G pluggable modules consume 10-15W each
• Density: QSFP-DD form factor limits port density
• Latency: Longer electrical traces add nanoseconds of delay

How CPO Solves These Problems

Challenge	Traditional Pluggable	CPO Approach
Power per 800G	~15W	~5W (60% reduction)
Electrical path	30-50mm	<5mm
Port density	Limited by module size	Optimized for chip-scale
Thermal management	Separate heat sink	Diamond thermal spreading

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CPO Architecture: Key Components

The Switch ASIC

The central switch processor (e.g., Broadcom Tomahawk 6 at 102.4Tbps or NVIDIA Quantum-X at 115.2Tbps) performs packet switching at extraordinary speeds. These chips contain hundreds of SerDes lanes operating at 100G or 200G.

Optical Engines

Each optical engine contains:

PIC (Photonic Integrated Circuit)

• Silicon photonics chip with optical modulators, detectors, waveguides
• Typically 8-16 channels at 100G or 200G each
• Handles actual light transmission/reception

EIC (Electronic Integrated Circuit)

• CMOS driver and TIA circuitry
• Converts electrical signals from the switch ASIC to optical signals
• Usually fabricated at 65nm or more advanced nodes

The Thermal Challenge

With optical engines consuming 50-100W and switch ASICs consuming 500W+ in the same package, thermal management becomes critical:

• Diamond substrate spreads heat across the package
• BDD (Boron-Doped Diamond) lids absorb EMI while conducting heat
• Micro-channel cooling may be integrated for extreme power densities

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Industry Adoption Timeline

Year	Milestone
2019	CPO concept demonstrated at OFC
2022	Broadcom announces Bailly 51.2T CPO switch
2024	First customer deliveries of CPO switches
2025	NVIDIA Spectrum-X Photonics announced at GTC
2025	Broadcom Tomahawk 6 (102.4T) with CPO support

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Key Players and Their Approaches

Broadcom

• Platform: Partnered with Google for custom CPO modules
• Optical Engine: Proprietary 6.4Tbps silicon photonics engines
• Integration: 8 optical engines per switch

NVIDIA

• Platform: TSMC COUPE (Compact Ultra-dense Photonics Engine)
• Technology: SoIC-X 3D stacking for PIC+EIC chiplets
• Products: Spectrum-X Photonics (Ethernet), Quantum-X Photonics (InfiniBand)

Chinese Ecosystem

• H3C: 51.2T CPO switch for domestic AI clusters

• 华为: Developing proprietary CPO solutions
• 华工正源: ELSFP modules compliant with OIF-ELSFP-02.0

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ELSFP: The External Light Source Alternative

Not all optical integration follows the CPO approach. ELSFP (External Light Source Fixed Pointer) modules place lasers outside the switch package, connected via fiber arrays.

Characteristic	CPO	ELSFP
Laser location	Inside package	External module
Serviceability	Limited (requires module replacement)	Field-replaceable lasers
Thermal coupling	Direct to diamond	Through fiber coupling
Typical use case	High-density AI clusters	Long-haul, metro networks

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What’s Next

CPO adoption is accelerating as:

1. AI cluster scale drives demand for lower power and higher density
2. 102.4T and 204.8T switches become mainstream
3. Standardization (OIF, IEEE 802.3) enables multi-vendor interoperability
4. Manufacturing yields improve for silicon photonics

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Related Terms

• PIC: Photonic Integrated Circuit - the silicon photonics chip with optical components
• EIC: Electronic Integrated Circuit - the CMOS driver/TIA circuitry
• ELSFP: External Light Source Fixed Pointer - separate laser module format
• SerDes: Serializer/Deserializer - high-speed interface between ASIC and optics
• COUPE: TSMC’s Compact Ultra-dense Photonics Engine platform

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