Understanding Optical Engine Architecture: PIC, EIC, and Chiplets

The Chiplet Revolution in Optics

Traditional photonic integrated circuits (PICs) were monolithic—a single silicon chip containing all optical components. However, as optical systems grew more complex, the limitations of monolithic integration became apparent:

• Yield: A defect in any component ruins the entire chip
• Process: Optical and electronic components require different fabrication steps
• Scalability: Large chips are expensive and lower yield

The solution? Chiplets—breaking complex systems into smaller, specialized dies that are packaged together.

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Two Chips, One Mission

In modern optical engines like NVIDIA’s COUPE platform, the system is divided into:

PIC: The Photonic Integrated Circuit

The PIC is a silicon photonics chip that handles all optical functions:

Core Components:

• Grating couplers - Couple light in/out of the chip from fiber
• Waveguides - Route light on-chip (similar to copper traces for electrical signals)
• Modulators - Encode data onto light (typically micro-ring modulators at 100-200G)
• Detectors - Convert received light back to electrical signals
• WDM multiplexers - Combine multiple wavelengths onto one fiber

Scale:

• Typical PIC size: 5mm × 5mm to 20mm × 20mm
• Channel count: 8, 16, or 32 channels per PIC
• Data rate: 100G or 200G per channel

EIC: The Electronic Integrated Circuit

The EIC contains the CMOS circuitry that drives the PIC:

Functions:

• Driver amplifiers - Boost signals to drive optical modulators
• TIA (Transimpedance Amplifier) - Amplify detector currents to voltage
• SerDes - Serialize/deserialize data between the switch ASIC and optics
• Control logic - Configure and monitor the optical engine

Technology:

• Typically fabricated at 65nm or 40nm CMOS
• Often uses TSMC’s SoIC-X 3D stacking to attach directly to PIC
• Size: Usually smaller than PIC, often 10mm × 10mm or less

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Heterogeneous Integration: The Key Enabler

TSMC COUPE Platform

NVIDIA’s optical engines use TSMC’s COUPE (Compact Ultra-dense Photonics Engine) technology:

1. SoIC-X Packaging - TSMC’s chiplet-stacking technology enables:

   • Face-to-face bonding of PIC and EIC
   • Ultra-short electrical connections (<100μm)
   • High-bandwidth density between chips

2. Benefits of this approach:

   • Bandwidth: 2Tbps per millimeter of interface width
   • Latency: Sub-nanosecond switch-to-optics delay
   • Power: Lower drive voltages due to short traces

Cross-Section View

An optical engine cross-section shows the layered structure:

┌─────────────────────────────────┐
│   EIC (CMOS Driver/TIA)         │  ← Electronic functions
├─────────────────────────────────┤
│   PIC (Silicon Photonics)       │  ← Optical functions
├─────────────────────────────────┤
│   Diamond Heat Spreader (6C)    │  ← Thermal management
├─────────────────────────────────┤
│   Substrate / Switch Package    │
└─────────────────────────────────┘

The diamond heat spreader is critical—heat must flow from both the EIC and PIC through the interface and into the diamond, which spreads it across a large area.

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Diamond’s Role in Chiplet-Based Optical Engines

Thermal Challenges

With both PIC and EIC generating heat in a small footprint:

• PIC: Laser diodes, modulators, detectors all generate heat
• EIC: CMOS switching at high frequencies creates thermal hotspots
• Package-level: 50-100W in a 20mm × 20mm area

Diamond Solutions from 6C

Component	6C Product	Benefit
PIC lid	Diamond IC Packaging Lid	EMI absorption + thermal spreading
EIC lid	BDD Heat Spreader	Tunable EMI absorption + thermal conductivity
MCM baseplate	Cu-Metallized Diamond	Cu routing + 2000+ W/m·K thermal conductivity

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Multiple PICs Per Switch

A high-bandwidth switch doesn’t use just one optical engine—it uses multiple PICs:

Example: Broadcom Tomahawk 6 (102.4T)

• 512 × 200G channels = 102.4Tbps total bandwidth
• May use 16-32 PICs, each handling 32 channels
• Each PIC paired with its own EIC

Example: NVIDIA Quantum-X (115.2T)

• 2 CPO modules per switch
• 3 silicon photonic engines (SPEs) per module
• 18 SPEs total per switch

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Why Not Just Monolithic?

Factor	Monolithic PIC	Chiplet Approach
Yield	Lower (one defect kills chip)	Higher (known-good die)
Process	Complex (mixed signal)	Simpler (separated)
Scalability	Limited by reticle size	Scalable via multiple chips
Testability	Difficult at wafer level	Tested before packaging
Flexibility	Fixed configuration	Mix and match

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The Future: More Integration

Even with chiplets, the industry is pushing for more integration:

• 3D stacking: Both PIC and EIC stacked vertically
• Optical I/O: Direct optical connection to processor chips
• Co-packaging with GPUs: Optical engines adjacent to AI accelerators

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Related Terms

• COUPE: Compact Ultra-dense Photonics Engine - TSMC’s platform for heterogeneous integration
• SoIC: System-on-Integrated-Chips - TSMC’s chiplet-stacking technology
• SerDes: Serializer/Deserializer - converts parallel data to high-speed serial
• TIA: Transimpedance Amplifier - amplifies detector currents
• MRM: Micro-ring Modulator - compact optical modulator

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